1. Field of the Invention
The present invention generally relates to a mask layout and in particular to optimizing two-dimensional features on a mask layout using interpretation filtering before optical proximity correction.
2. Description of the Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit on a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto a template (i.e. a mask or reticle, hereinafter called a mask), and then to the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes, which will embody the devices themselves on the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. One way to do this is to use the process of optical lithography in which the layout is first transferred onto a physical template, which is in turn used to optically project the layout onto a silicon wafer.
In transferring the layout to a physical template, a mask (usually a quartz plate coated with chrome) is generally created for each layer of the integrated circuit design. This is done by inputting the data representing the layout design for that layer into a device such, as an electron beam machine, which writes the integrated circuit layout pattern into the mask material.
These masks are then used to optically project the layout onto a silicon wafer coated with photo-resist material. For each layer of the design, a light is shone on the mask corresponding to that layer. This light passes through the clear regions of the mask, whose image exposes the underlying photo-resist layer. The light is blocked by the opaque regions of the mask, thereby leaving the underlying portion of the photo-resist layer unexposed. The exposed photo-resist layer is then developed, typically, through chemical removal of the exposed/non-exposed regions of the photo-resist layer. The end result is a semiconductor wafer coated with a photo-resist layer exhibiting a desired pattern, which defines the geometries, features, lines and shapes of that layer. This process is then repeated for each layer of the design.
FIG. 1A illustrates a standard mask layout feature 100 that can be used to form a transistor. Diffraction effects, photo-resist processing effects, other processing effects, and/or combinations of one or more effects can cause distortions of mask layout feature 100 during lithography. FIG. 1B illustrates that such distortions can cause an ideal printed line end 101 of mask layout feature 100 to transfer to a wafer as actual printed line end 102. Notably, actual printed line end 102 is shorter and exhibits more rounded corners than ideal printed line end 101. Unfortunately, these distortions can cause adverse effects on the functioning of a printed circuit including feature 100.
To solve the problem associated with lithographic distortions, optical proximity correction features, e.g. hammerheads or serifs, can be added to the layout. FIG. 2A illustrates exemplary serifs 201 that can be added to mask layout feature 100 (FIG. 1A). FIG. 2B illustrates that serifs 201 can cause ideal printed line end 106 to transfer to a wafer as actual printed line end 202. Note that actual printed line end 202 is substantially the same length as ideal printed line end 106, thereby resolving the line end shortening problem.
Unfortunately, actual printed line end 202 now exhibits other undesirable characteristics. Specifically, this line end has a bulbous feature in addition to a pinch point. This phenomenon is sometimes called Q-tipping because of the resulting shape. This phenomenon is caused by constructive interference nodes, which are created during the lithographic process and occurs around all two-dimensional features. The effect of Q-tipping (i.e. the offset from the ideal printed line edge) can be significant, e.g. 10% or more of the line width per side, thereby resulting in an 80 nm wide pinch point for a nominally 100 nm wide line. Therefore, in features formed in close proximity, bridging between features may occur because of their bulbous portions.
The pinched portions of the line ends can also become problematic. Specifically, in a standard IC manufacturing process, variations in through-process effects can exacerbate the pinching. Through-process effects can include, for example, the dose and focus variation from the nominal conditions provided by a photolithography stepper as well as the variations in the thickness or other characteristics (e.g. bake temperature, chemical composition, water quality, ambient temperature, etc.) of a photo-resist used on a wafer. Therefore, for example, if a contact is to be formed underneath a line end, then the pinched portion of the line end in combination with through-process variations could result in an open circuit for that contact.
These through-process variations can occur despite the best intentions of the manufacturer. Setting and resetting a tool to correct for such through-process effects can take significant time, e.g. on the order of 12 hours. Logically, the less time needed to perform maintenance for such through-process variations can improve the cost effectiveness of the equipment. That is, the equipment is on-line more, thereby producing more products per unit of time.
Therefore, a need arises for a technique to more effectively correct for lithographic distortions while providing a technique that is less sensitive to (i.e. more tolerant of) through-process effects.